We propose a design optimization flow for a high-speed and low-power operational transconductance amplifier (OTA) using a gm/ID lookup table design methodology in scaled CMOS. This methodology advantages from using gm/ID as a primary design parameter to consider all operation regions including strong, moderate, and weak inversion regions, and enables the lowest power design. SPICE-based lookup table approach is employed to optimize the operation region specified by the gm/ID with sufficient accuracy for short-channel transistors. The optimized design flow features 1) a proposal of the worst-case design scenario for specification and gm/ID lookup table generations from worst-case SPICE simulations, 2) an optimization procedure accomplished by the combination of analytical and simulation-based approaches in order to eliminate tweaking of circuit parameters, and 3) an additional use of gm/ID subplots to take second-order effects into account. A gain-boosted folded-cascode OTA for a switched capacitor circuit is adopted as a target topology to explore the effectiveness of the proposed design methodology for a circuit with complex topology. Analytical expressions of the gain-boosted folded-cascode OTA in terms of DC gain, frequency response and output noise are presented, and detailed optimization of gm/IDs as well as circuit parameters are illustrated. The optimization flow is verified for the application to a residue amplifier in a 10-bit 125 MS/s pipeline A/D converter implemented in a 0.18 µm CMOS technology. The optimized circuit satisfies the required specification for all corner simulations without additional tweaking of circuit parameters. We finally explore the possibility of applying this design methodology as a technology migration tool, and illustrate the failure analysis by comparing the differences in the gm/ID characteristics.

The earlier the stage where we perform low power design, the higher the dynamic power reduction we achieve. In this paper, we focus on reducing switching activity in high-level synthesis, especially, in the problem of functional module binding, bus binding or register binding. We propose an effective low power bus binding algorithm based on the table decomposition method, to reduce switching activity. The proposed algorithm is based on the decomposition of the original problem into sub-problems by exploiting the optimal substructure. As a result, it finds an optimal or close-to-optimal binding solution with less computation time. Experimental results show the proposed method obtains a solution 2.3-22.2% closer to optimal solution than one with a conventional heuristic method, 8.0-479.2 times faster than the optimal one (at a threshold value of 1.0E+9).

This paper presents the design of a driver amplifier (DA) for a cordless mouse application, operating at the 2.4 GHz ISM unlicensed band. The DA is a single-ended topology, and is composed of two stages: the first stage is a cascode amplifier to provide high gain and good input-output isolation, while the output stage is a simple common source amplifier that adopts a novel current reuse scheme to reduce the DC bias current by half. The DA implemented in a 0.18 µm CMOS process has a 16 dB gain at 2.4 GHz, and it can drive a 3 dBm to the antenna with an output stage drain efficiency of 31% and a power-added efficiency (PAE) of 20% while drawing 4.5 mA from a 1.8 V supply.

A novel data serializer is proposed for use in mobile TFT-LCD driver ICs. The proposed data serializer adopting hierarchical switching and repeater/separator schemes provides 82% power reduction and 27% speed improvement with 27% area saving. Measured overall power consumption of a TFT-LCD driver IC with the proposed data serializer was reduced by as much as 49%.

A 9-bit 100-MS/s successive approximation register (SAR) ADC with low power and small area has been implemented in 65-nm CMOS technology. A tri-level charge redistribution technique is proposed to reduce DAC switching energy and settling time. By connecting bottom plates of differential capacitor arrays for charge sharing, extra reference voltage is avoided. Two reference voltages charging and discharging the capacitors are chosen to be supply voltage and ground in order to save energy and achieve a rail-to-rail input range. Split capacitor arrays with mismatch calibration are implemented for small area and small input capacitance without linearity degradation. The ADC achieves a peak SNDR of 53.1 dB and consumes 1.46 mW from a 1.2-V supply, resulting in a figure of merit (FOM) of 39 fJ/conversion-step. The total active area is 0.012 mm2 and the input capacitance is 180 fF.

Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption. Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the control signals specified by designers are used, and the effectiveness of the clock gating depends on the specified control signals. In the research, we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection. We formalize the control signal selection using linear formulae and devise an optimization method based on BDD. The method is effective for circuits with a lot of shared candidates by different registers. The method is applied to counter circuits to check the co-relation with power simulation results and a set of benchmark circuits. 19.1-71.9% power reduction has been found on counter circuitsafter layout and 2.3-18.0% cost reduction on benchmark circuits.

A Real-time Capacitor Compensation (RCC) scheme is proposed for low power and continuous communication in the wearable inductive coupling transceiver. Since inductance values of wearable inductor vary dynamically with deterioration of its communication characteristics, the inductance value is monitored and its resonance frequency is adjusted by additive parallel/serial capacitors in real time. RLC Bridge for detection of the inductance variations and the Dual-edge Sampling Comparator for recognition of the variance direction are proposed. It is implemented in a 0.18 µm CMOS technology, and it occupies a 12.7 mm2 chip area. The proposed transceiver consumes only 426.6 µW at 4 Mbps data rate. The compensation time takes 4.78 µs, including 3 µs of detection and 1.78 µs for compensation process in worst case.

The principles for good design of battery-aware voltage scheduling algorithms for both aperiodic and periodic task sets on dynamic voltage scaling (DVS) systems are presented. The proposed algorithms are based on greedy heuristics suggested by several battery characteristics and Lagrange multipliers. To construct the proposed algorithms, we use the battery characteristics in the early stage of scheduling more properly. As a consequence, the proposed algorithms show superior results on synthetic examples of periodic and aperiodic tasks from the task sets which are excerpted from the comparative work, on uni- and multi-processor platforms, respectively. In particular, for some large task sets, the proposed algorithms enable previously unschedulable task sets due to battery exhaustion to be schedulable.

The noise performances under AWGN channel of the IF-derivative and the quadrature differential FM discriminators, which are widely utilized in modern low power wireless radios, are analyzed and compared. The analysis relies upon the time-domain multi-sinusoidal representation of the noise that facilitates accurate and closed-form analytical SNR characteristics. Derivation of the SNR equations is detailed and discussion based on the analysis results is given to provide insights into the discriminators' performance limitation where it is demonstrated that the differential scheme is considerably more advantageous. Simulated SNR characteristics of practical continuous-phase frequency shift keying (CPFSK) systems using both the FM discriminators are presented as analysis verification.

In this paper a new electromagnetic (EM) interference analysis is proposed using the total harmonic distortion (THD) measurement of the audio signal by the 900 MHz cordless telephones. The cordless telephone network in 900 MHz was built up to be weak in EM interference. 400 and 800 Hz of the sine-wave signal were used in transmitter (TX) system, and the receiver (RX) system was exposed to the EM interference. The THD value varies as the level of the exposed EM interference changes. The model of the cordless telephone also affects the THD value. By using fluctuation of the THD value depending on the amount of the exposure, the threshold value of the interference electric field strength was derived. Based on the derived threshold value of the electric field strength, validity of the regulation value for low power radio devices by CISPR 22 [CLASS B] and FCC is discussed.

We detail a self synchronous field programmable gate array (SSFPGA) with dual-pipeline (DP) architecture to conceal pre-charge time for dynamic logic, and its throughput optimization by using pipeline alignment implemented on benchmark circuits. A self synchronous LUT (SSLUT) consists of a three input tree-type structure with 8 bits of SRAM for programming. A self synchronous switch box (SSSB) consists of both pass transistors and buffers to route signals, with 12 bits of SRAM. One common block with one SSLUT and one SSSB occupies 2.2 Mλ2 area with 35 bits of SRAM, and the prototype SSFPGA with 3430 (1020) blocks is designed and fabricated using 65 nm CMOS. Measured results show at 1.2 V 430 MHz and 647 MHz operation for a 3 bit ripple carry adder, without and with throughput optimization, respectively. We find that using the proposed pipeline alignment techniques we can perform at maximum throughput of 647 MHz in various benchmarks on the SSFPGA. We demonstrate up to 56.1 times throughput improvement with our pipeline alignment techniques. The pipeline alignment is carried out within the number of logic elements in the array and pipeline buffers in the switching matrix.

A low power impulse radio ultra-wideband (IR-UWB) receiver for DC-960 MHz band is proposed in this paper. The proposed receiver employs multiple DC power-free charge-domain sampling correlators to eliminate the need for phase synchronization. To alleviate BER degradation due to an increased charge injection in a subtraction operation in the sampling correlator than that of an addition operation, a comparator with variable threshold (=offset) voltage is used, which enables an addition-only operation. The developed receiver fabricated in 1.2 V 65 nm CMOS achieves the lowest energy consumption of 17.6 pJ/bit at 100 Mbps in state-of-the-art correlation-based UWB receivers.

In this paper, an ultra low power analog front-end for EPCglobal Class 1 Generation 2 RFID tag is presented. The proposed RFID tag removes the need for high frequency clock and counters used in conventional tags, which are the most power hungry blocks. The proposed clock-free decoder employs an analog integrator with an adaptive current source that provides a uniform decoding margin regardless of the data rate and a link frequency extractor based on a relaxation oscillator that generates frequency used for backscattering. A dual supply voltage scheme is also employed to increase the power efficiency of the tag. In order to improve the tolerance of the proposed circuit to environmental variations, a self-calibration circuit is proposed. The proposed RFID analog front-end circuit is designed and simulated in 0.25 µm CMOS, which shows that the power consumption is reduced by an order magnitude compared to the conventional RFID tags, without losing immunity to environmental variations.

Architecture of a low power Ternary Content Addressable Memory (TCAM) is proposed. The TCAM is a powerful engine for search and sort processing, but it has two serious problems, large power consumption and large power line noise. To solve these problems, we have developed a charge recycling scheme for match lines and search lines. A combination of the newly introduced PMOS CAM cell together with the conventional NMOS CAM cell realizes match line charge recycling. A checkerboard arrangement of the NMOS and the PMOS cell array enables search line charge recycling. By using these technologies, the power consumption of the TCAM can be reduced to 50% of conventional designs, and as a result, the power line noise is also reduced. An experimental chip has been fabricated in 180-nm 6-metal process. The power consumption of this chip is 6.3 fJ/bit/search, which is half of the conventional scheme.

A novel signal transition detector design using as few as 8 transistors is presented. The proposed design cleverly exploits the property of a specific internal state transition to mitigate the voltage degradation problem by employing only one extra transistor. It is thus capable of supporting level intact output signals and eliminating DC power consumption in the trailing buffer. The proposed design, featuring low circuit complexity and low power consumption, is considered useful for applications in self-timed circuits. Simulation results show that, when compared with other pass transistor logic based counterpart designs, as much as 46% savings in power and 28% in area can be achieved by the proposed design.

Multiple supply voltage (MSV) assignment is a highly effective means of reducing power consumption. Many existing algorithms perform very well for power reduction. However, they do not handle the area issue of level shifters. In some cases, although one gets a superior result to reduce the power consumption, but many extra level shifters are needed to add so that the circuit area will be over the specification. In this paper, we present an effective integer linear programming (ILP)-based MSV assignment approach to solve two problems with different objectives. For the objective of power reduction under timing constraint, compared with GECVS algorithm, the power consumption obtained by our proposed approach can be further reduced 0 to 5.46% and the number of level shifters is improved 16.31% in average. For the objective of power reduction under constraints of both timing and area of level shifters, the average improvement of power consumption obtained by our algorithm is still better than GECVS while reducing the number of level shifters by 22.92% in average. In addition, given a constraint of total power consumption, our algorithm will generate a design having minimum circuit delay. Experimental results show that the proposed ILP-based MSV assignment algorithm solves different problems flexibly.

Proposed in this paper is a low power BIST architecture using the pattern mapping method based on the transition freezing method. The transition freezing method generates frozen patterns dynamically according to the transition tendency of an LFSR. This leads to an average power reduction of 60%. However, the patterns have limitations of 100% fault coverage due to random resistant faults. Therefore, in this paper, those faults are detected by mapping useless patterns among frozen patterns to the patterns generated by an ATPG. Throughout the scheme, 100% fault coverage is achieved. Moreover, we have reduced the amount of applied patterns, the test time, and the power dissipation.

This paper presents an ultra-low-power single-chip sensor-node VLSI for wireless-sensor-network applications. A communication centric design approach has been introduced to reduce the power consumption of the RF circuits and the entire sensor network system, through a vertical cooperative design among circuits, architecture, and communication protocols. The sensor-node LSI features a synchronous media access control (MAC) protocol and integrates a transceiver, i8051 microcontroller, and dedicated MAC processor. The test chip occupies 33 mm2 in a 180-nm CMOS process, including 1.38 M transistors. It dissipates 58.0 µW under a network environment.

A new low voltage operation of high voltage switching technique, which is capable of reducing leakage current by an order of three compared to conventional circuits, has been developed for sub-1.8 V low voltage mobile NAND flash memory. In addition, by using the proposed high voltage switch, chip size scaling can be realized due to reduced a minimum required space between the N-wells of selected and unselected blocks for isolation. The proposed scheme is essential to achieve low power operation NAND Flash memory, especially for mobile electronics.

In this paper, we present an efficient low power scan test technique which simultaneously reduces both average and peak power consumption. The selective scan chain activation scheme removes unnecessary scan chain utilization during the scan shift and capture operations. Statistical scan cell reordering enables efficient scan chain removal. The experimental results demonstrated that the proposed method constantly reduces the average and peak power consumption during scan testing.